A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

Zhangcai Huang, Qin Luo, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    24 Citations (Scopus)

    Abstract

    In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW.

    Original languageEnglish
    Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
    Pages4069-4072
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris
    Duration: 2010 May 302010 Jun 2

    Other

    Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
    CityParis
    Period10/5/3010/6/2

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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  • Cite this

    Huang, Z., Luo, Q., & Inoue, Y. (2010). A CMOS sub-1-V nanopower current and voltage reference with leakage compensation. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 4069-4072). [5537636] https://doi.org/10.1109/ISCAS.2010.5537636