A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

Original languageEnglish
Title of host publicationProceedings of the Working Conference on Advanced Visual Interfaces, AVI' 10
Pages207-212
Number of pages6
DOIs
Publication statusPublished - 2010 Oct 21
EventInternational Conference on Advanced Visual Interfaces, AVI '10 - Rome, Italy
Duration: 2010 May 262010 May 28

Publication series

NameProceedings of the Workshop on Advanced Visual Interfaces AVI

Conference

ConferenceInternational Conference on Advanced Visual Interfaces, AVI '10
CountryItaly
CityRome
Period10/5/2610/5/28

Keywords

  • LDPC
  • Message passing algorithm

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction

Fingerprint Dive into the research topics of 'A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm'. Together they form a unique fingerprint.

Cite this