A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Ji Wen; Yuta Abe; Takeshi Lkenaga; Satoshi Goto

doi:10.1145/1366110.1366161

A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Ji Wen^*, Yuta Abe, Takeshi Lkenaga, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

Original language	English
Title of host publication	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages	207-212
Number of pages	6
DOIs	https://doi.org/10.1145/1366110.1366161
Publication status	Published - 2008
Event	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL Duration: 2008 Mar 4 → 2008 Mar 6

Other

Other	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
City	Orlando, FL
Period	08/3/4 → 08/3/6

Keywords

LDPC
Message passing algorithm

ASJC Scopus subject areas

Engineering(all)

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10.1145/1366110.1366161

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title = "A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm",

abstract = "A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.",

keywords = "LDPC, Message passing algorithm",

author = "Ji Wen and Yuta Abe and Takeshi Lkenaga and Satoshi Goto",

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doi = "10.1145/1366110.1366161",

language = "English",

isbn = "9781595939999",

pages = "207--212",

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AU - Lkenaga, Takeshi

AU - Goto, Satoshi

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Y1 - 2008

N2 - A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

AB - A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

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KW - Message passing algorithm

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BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

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ER -

A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Abstract

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Keywords

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