A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Ji Wen, Yuta Abe, Takeshi Lkenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages207-212
Number of pages6
DOIs
Publication statusPublished - 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL
Duration: 2008 Mar 42008 Mar 6

Other

OtherGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CityOrlando, FL
Period08/3/408/3/6

Keywords

  • LDPC
  • Message passing algorithm

ASJC Scopus subject areas

  • Engineering(all)

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