Abstract
A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
| Pages | 207-212 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2008 |
| Event | GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL Duration: 2008 Mar 4 → 2008 Mar 6 |
Other
| Other | GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 |
|---|---|
| City | Orlando, FL |
| Period | 08/3/4 → 08/3/6 |
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Keywords
- LDPC
- Message passing algorithm
ASJC Scopus subject areas
- Engineering(all)
Cite this
A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm. / Wen, Ji; Abe, Yuta; Lkenaga, Takeshi; Goto, Satoshi.
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2008. p. 207-212.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm
AU - Wen, Ji
AU - Abe, Yuta
AU - Lkenaga, Takeshi
AU - Goto, Satoshi
PY - 2008
Y1 - 2008
N2 - A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
AB - A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
KW - LDPC
KW - Message passing algorithm
UR - http://www.scopus.com/inward/record.url?scp=56749140685&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=56749140685&partnerID=8YFLogxK
U2 - 10.1145/1366110.1366161
DO - 10.1145/1366110.1366161
M3 - Conference contribution
SN - 9781595939999
SP - 207
EP - 212
BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
ER -