Abstract
This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| Pages | 250-255 |
| Number of pages | 6 |
| Publication status | Published - 2004 |
| Event | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama Duration: 2004 Jan 27 → 2004 Jan 30 |
Other
| Other | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 |
|---|---|
| City | Yokohama |
| Period | 04/1/27 → 04/1/30 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. / Miyaoka, Yuichiro; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 250-255.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A cosynthesis algorithm for application specific processors with heterogeneous datapaths
AU - Miyaoka, Yuichiro
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2004
Y1 - 2004
N2 - This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
AB - This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.
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UR - http://www.scopus.com/inward/citedby.url?scp=2442437902&partnerID=8YFLogxK
M3 - Conference contribution
SP - 250
EP - 255
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ER -