A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

School of Fundamental Science and Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

Original language	English
Pages	250-255
Number of pages	6
Publication status	Published - 2004 Jun 1
Event	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 2004 Jan 27 → 2004 Jan 30

Conference

Conference	Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country	Japan
City	Yokohama
Period	04/1/27 → 04/1/30

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A cosynthesis algorithm for application specific processors with heterogeneous datapaths'. Together they form a unique fingerprint.

Cite this

A cosynthesis algorithm for application specific processors with heterogeneous datapaths. / Miyaoka, Yuichiro; Togawa, Nozomu ; Yanagisawa, Masao; Ohtsuki, Tatsuo.

2004. 250-255 Paper presented at Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, Japan.

Research output: Contribution to conference › Paper › peer-review

@conference{a8c277df3c984fb6a804a2eda8a873e2,

title = "A cosynthesis algorithm for application specific processors with heterogeneous datapaths",

abstract = "This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.",

author = "Yuichiro Miyaoka and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2004",

month = jun,

day = "1",

language = "English",

pages = "250--255",

note = "Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 ; Conference date: 27-01-2004 Through 30-01-2004",

}

TY - CONF

T1 - A cosynthesis algorithm for application specific processors with heterogeneous datapaths

AU - Miyaoka, Yuichiro

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2004/6/1

Y1 - 2004/6/1

N2 - This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

AB - This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

UR - http://www.scopus.com/inward/record.url?scp=2442437902&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2442437902&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:2442437902

SP - 250

EP - 255

T2 - Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004

Y2 - 27 January 2004 through 30 January 2004

ER -