A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen; Xiao Xu; Toshihiko Yoshimasu

doi:10.1109/APMC.2017.8251363

A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen, Xiao Xu, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

Original language	English
Title of host publication	2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5-8
Number of pages	4
Volume	Part F134147
ISBN (Electronic)	9781538606407
DOIs	https://doi.org/10.1109/APMC.2017.8251363
Publication status	Published - 2018 Jan 8
Event	2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia Duration: 2017 Nov 13 → 2017 Nov 16

Other

Other	2017 IEEE Asia Pacific Microwave Conference, APMC 2017
Country	Malaysia
City	Kuala Lumpur
Period	17/11/13 → 17/11/16

Keywords

broadband
high P1dB
low insertion loss
SOI
SPDT switch IC

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APMC.2017.8251363

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Cite this

Chen, C, Xu, X & Yoshimasu, T 2018, A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS. in 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. vol. Part F134147, Institute of Electrical and Electronics Engineers Inc., pp. 5-8, 2017 IEEE Asia Pacific Microwave Conference, APMC 2017, Kuala Lumpur, Malaysia, 17/11/13. https://doi.org/10.1109/APMC.2017.8251363

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abstract = "A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.",

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N2 - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

AB - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

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