A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen; Xiao Xu; Toshihiko Yoshimasu

doi:10.1109/APMC.2017.8251363

A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen, Xiao Xu, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

Original language	English
Title of host publication	2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
Editors	Idnin Pasya
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5-8
Number of pages	4
ISBN (Electronic)	9781538606407
DOIs	https://doi.org/10.1109/APMC.2017.8251363
Publication status	Published - 2017 Jun 28
Event	2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia Duration: 2017 Nov 13 → 2017 Nov 16

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	2017 IEEE Asia Pacific Microwave Conference, APMC 2017
Country	Malaysia
City	Kuala Lumpur
Period	17/11/13 → 17/11/16

Keywords

SOI
SPDT switch IC
broadband
high P1dB
low insertion loss

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APMC.2017.8251363

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A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS. / Chen, Cuilin; Xu, Xiao; Yoshimasu, Toshihiko.

2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. ed. / Idnin Pasya. Institute of Electrical and Electronics Engineers Inc., 2017. p. 5-8 (Asia-Pacific Microwave Conference Proceedings, APMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, C, Xu, X & Yoshimasu, T 2017, A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS. in I Pasya (ed.), 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings. Asia-Pacific Microwave Conference Proceedings, APMC, Institute of Electrical and Electronics Engineers Inc., pp. 5-8, 2017 IEEE Asia Pacific Microwave Conference, APMC 2017, Kuala Lumpur, Malaysia, 17/11/13. https://doi.org/10.1109/APMC.2017.8251363

@inproceedings{935619d277e0437f8a3555d56292a877,

title = "A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS",

abstract = "A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.",

keywords = "SOI, SPDT switch IC, broadband, high P1dB, low insertion loss",

author = "Cuilin Chen and Xiao Xu and Toshihiko Yoshimasu",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Asia Pacific Microwave Conference, APMC 2017 ; Conference date: 13-11-2017 Through 16-11-2017",

year = "2017",

month = jun,

day = "28",

doi = "10.1109/APMC.2017.8251363",

language = "English",

series = "Asia-Pacific Microwave Conference Proceedings, APMC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "5--8",

editor = "Idnin Pasya",

booktitle = "2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings",

}

TY - GEN

T1 - A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

AU - Chen, Cuilin

AU - Xu, Xiao

AU - Yoshimasu, Toshihiko

PY - 2017/6/28

Y1 - 2017/6/28

N2 - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

AB - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

KW - SOI

KW - SPDT switch IC

KW - broadband

KW - high P1dB

KW - low insertion loss

UR - http://www.scopus.com/inward/record.url?scp=85044750434&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85044750434&partnerID=8YFLogxK

U2 - 10.1109/APMC.2017.8251363

DO - 10.1109/APMC.2017.8251363

M3 - Conference contribution

AN - SCOPUS:85044750434

T3 - Asia-Pacific Microwave Conference Proceedings, APMC

SP - 5

EP - 8

BT - 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings

A2 - Pasya, Idnin

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE Asia Pacific Microwave Conference, APMC 2017

Y2 - 13 November 2017 through 16 November 2017

ER -

A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Abstract

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Keywords

ASJC Scopus subject areas

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