A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen, Xiao Xu, Toshihiko Yoshimasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

Original languageEnglish
Title of host publication2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5-8
Number of pages4
VolumePart F134147
ISBN (Electronic)9781538606407
DOIs
Publication statusPublished - 2018 Jan 8
Event2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia
Duration: 2017 Nov 132017 Nov 16

Other

Other2017 IEEE Asia Pacific Microwave Conference, APMC 2017
CountryMalaysia
CityKuala Lumpur
Period17/11/1317/11/16

Keywords

  • broadband
  • high P1dB
  • low insertion loss
  • SOI
  • SPDT switch IC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Chen, C., Xu, X., & Yoshimasu, T. (2018). A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS. In 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings (Vol. Part F134147, pp. 5-8). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APMC.2017.8251363