A delay variation and floorplan aware high-level synthesis algorithm with body biasing

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    In this paper, we propose a delay variation and floorplan aware high-level synthesis algorithm with body biasing, which minimizes the average leakage energy of manufactured chips. To realize a floorplan-oriented high-level synthesis, we utilize a huddle-based distributed register architecture (HDR architecture), one of the DR architectures. HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit but can increase the latency. We assign CDFG nodes in critical paths to the huddles with larger expected leakage energy and those in non-critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 38.9% without latency and yield degradation compared with typical-case design with body biasing.

    Original languageEnglish
    Title of host publicationProceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
    PublisherIEEE Computer Society
    Pages75-80
    Number of pages6
    Volume2016-May
    ISBN (Electronic)9781509012138
    DOIs
    Publication statusPublished - 2016 May 25
    Event17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, United States
    Duration: 2016 Mar 152016 Mar 16

    Other

    Other17th International Symposium on Quality Electronic Design, ISQED 2016
    CountryUnited States
    CitySanta Clara
    Period16/3/1516/3/16

    Keywords

    • body biasing
    • delay variation
    • floorplan
    • high-level synthesis
    • interconnection delay

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

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  • Cite this

    Igawa, K., Shi, Y., Yanagisawa, M., & Togawa, N. (2016). A delay variation and floorplan aware high-level synthesis algorithm with body biasing. In Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016 (Vol. 2016-May, pp. 75-80). [7479179] IEEE Computer Society. https://doi.org/10.1109/ISQED.2016.7479179