A delay-variation-aware high-level synthesis algorithm for RDR architectures

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    5 Citations (Scopus)

    Abstract

    As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.

    Original languageEnglish
    Pages (from-to)81-90
    Number of pages10
    JournalIPSJ Transactions on System LSI Design Methodology
    Volume7
    DOIs
    Publication statusPublished - 2014

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    Scheduling
    High level synthesis
    Silicon

    Keywords

    • Distributed-register architecture
    • High-level synthesis
    • Post-silicon tuning
    • Process and delay variation

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications

    Cite this

    @article{123a7ca5511046b68522ef5b15779989,
    title = "A delay-variation-aware high-level synthesis algorithm for RDR architectures",
    abstract = "As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9{\%} compared with the conventional approach.",
    keywords = "Distributed-register architecture, High-level synthesis, Post-silicon tuning, Process and delay variation",
    author = "Yuta Hagio and Masao Yanagisawa and Nozomu Togawa",
    year = "2014",
    doi = "10.2197/ipsjtsldm.7.81",
    language = "English",
    volume = "7",
    pages = "81--90",
    journal = "IPSJ Transactions on System LSI Design Methodology",
    issn = "1882-6687",
    publisher = "Information Processing Society of Japan",

    }

    TY - JOUR

    T1 - A delay-variation-aware high-level synthesis algorithm for RDR architectures

    AU - Hagio, Yuta

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2014

    Y1 - 2014

    N2 - As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.

    AB - As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.

    KW - Distributed-register architecture

    KW - High-level synthesis

    KW - Post-silicon tuning

    KW - Process and delay variation

    UR - http://www.scopus.com/inward/record.url?scp=84962143526&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84962143526&partnerID=8YFLogxK

    U2 - 10.2197/ipsjtsldm.7.81

    DO - 10.2197/ipsjtsldm.7.81

    M3 - Article

    AN - SCOPUS:84962143526

    VL - 7

    SP - 81

    EP - 90

    JO - IPSJ Transactions on System LSI Design Methodology

    JF - IPSJ Transactions on System LSI Design Methodology

    SN - 1882-6687

    ER -