A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

Nozomu Togawa, Koji Ara, Masao Yanagisawa, Tatsuo Ohtsuki

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    Abstract

    This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    Original languageEnglish
    Pages (from-to)473-481
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE82-A
    Issue number3
    Publication statusPublished - 1999

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    Keywords

    • Logic depth
    • Logic-block
    • Lookup table
    • Technology mapping

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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