Abstract
This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
| Original language | English |
|---|---|
| Pages (from-to) | 473-481 |
| Number of pages | 9 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E82-A |
| Issue number | 3 |
| Publication status | Published - 1999 Jan 1 |
Keywords
- Logic depth
- Logic-block
- Lookup table
- Technology mapping
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
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Cite this
Togawa, N., Ara, K., Yanagisawa, M., & Ohtsuki, T. (1999). A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82-A(3), 473-481.