### Abstract

This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d _{c}. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

Original language | English |
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Pages (from-to) | 473-481 |

Number of pages | 9 |

Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

Volume | E82-A |

Issue number | 3 |

Publication status | Published - 1999 |

### Fingerprint

### Keywords

- Logic depth
- Logic-block
- Lookup table
- Technology mapping

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Hardware and Architecture
- Information Systems

### Cite this

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E82-A*(3), 473-481.

**A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs.** / Togawa, Nozomu; Ara, Koji; Yanagisawa, Masao; Ohtsuki, Tatsuo.

Research output: Contribution to journal › Article

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*, vol. E82-A, no. 3, pp. 473-481.

}

TY - JOUR

T1 - A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

AU - Togawa, Nozomu

AU - Ara, Koji

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 1999

Y1 - 1999

N2 - This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

AB - This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

KW - Logic depth

KW - Logic-block

KW - Lookup table

KW - Technology mapping

UR - http://www.scopus.com/inward/record.url?scp=0032661950&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032661950&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0032661950

VL - E82-A

SP - 473

EP - 481

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 3

ER -