A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM

This paper will describe a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAM's. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K × 8 full CMOS RAM has been developed with 2 μ m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in the speed performance, second poly-Si layer was replaced with a polycide (poly-Si + MoSi2) layer, thus offering a 50 ns address access time.