A dual-mode deblocking filter design for HEVC and H.264/AVC

Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16×16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16×16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200MHz in SMIC 65 nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60 fps. With filter reusing scheme, the universal design for the two standards saves 30% gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2% with skipping mode when the edges need not be filtered.

Original languageEnglish
Pages (from-to)1366-1375
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE96-A
Issue number6
DOIs
Publication statusPublished - 2013 Jun

Fingerprint

Filter Design
High Efficiency
Filter
Clocks
Count
Universal Design
Cycle
Video Compression
Video Coding
Image compression
Image coding
Power Consumption
Macros
Electric power utilization
Throughput
Filtering
Standards
Synthesis
Unit
Requirements

Keywords

  • Deblocking filter
  • Dual-mode
  • H.264/AVC
  • HD
  • HEVC
  • Low power
  • SHV

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

A dual-mode deblocking filter design for HEVC and H.264/AVC. / Li, Muchen; Zhou, Jinjia; Zhou, Dajiang; Peng, Xiao; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No. 6, 06.2013, p. 1366-1375.

Research output: Contribution to journalArticle

Li, Muchen ; Zhou, Jinjia ; Zhou, Dajiang ; Peng, Xiao ; Goto, Satoshi. / A dual-mode deblocking filter design for HEVC and H.264/AVC. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2013 ; Vol. E96-A, No. 6. pp. 1366-1375.
@article{b63d27d85d3241edb9ab4f3c413000dc,
title = "A dual-mode deblocking filter design for HEVC and H.264/AVC",
abstract = "As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16×16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16×16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200MHz in SMIC 65 nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60 fps. With filter reusing scheme, the universal design for the two standards saves 30{\%} gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2{\%} with skipping mode when the edges need not be filtered.",
keywords = "Deblocking filter, Dual-mode, H.264/AVC, HD, HEVC, Low power, SHV",
author = "Muchen Li and Jinjia Zhou and Dajiang Zhou and Xiao Peng and Satoshi Goto",
year = "2013",
month = "6",
doi = "10.1587/transfun.E96.A.1366",
language = "English",
volume = "E96-A",
pages = "1366--1375",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "6",

}

TY - JOUR

T1 - A dual-mode deblocking filter design for HEVC and H.264/AVC

AU - Li, Muchen

AU - Zhou, Jinjia

AU - Zhou, Dajiang

AU - Peng, Xiao

AU - Goto, Satoshi

PY - 2013/6

Y1 - 2013/6

N2 - As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16×16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16×16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200MHz in SMIC 65 nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60 fps. With filter reusing scheme, the universal design for the two standards saves 30% gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2% with skipping mode when the edges need not be filtered.

AB - As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16×16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16×16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200MHz in SMIC 65 nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60 fps. With filter reusing scheme, the universal design for the two standards saves 30% gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2% with skipping mode when the edges need not be filtered.

KW - Deblocking filter

KW - Dual-mode

KW - H.264/AVC

KW - HD

KW - HEVC

KW - Low power

KW - SHV

UR - http://www.scopus.com/inward/record.url?scp=84878553538&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878553538&partnerID=8YFLogxK

U2 - 10.1587/transfun.E96.A.1366

DO - 10.1587/transfun.E96.A.1366

M3 - Article

AN - SCOPUS:84878553538

VL - E96-A

SP - 1366

EP - 1375

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 6

ER -