A Fast 8K x 8 Mixed CMOS Static RAM

Hirofumi Shinohara, Kenji Anami, Tsutomu Yoshihara, Yoshio Kohno, Yoichi Akasaka, Shinpei Kayano, Yuji Kihara

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Abstract

This paper describes a fast 8K x 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard baids around the wells. A 2-μm design rule combined with the double level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 μm2and design of the die in 34.3 mm2.

Original languageEnglish
Pages (from-to)1792-1796
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume32
Issue number9
DOIs
Publication statusPublished - 1985 Sep

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shinohara, H., Anami, K., Yoshihara, T., Kohno, Y., Akasaka, Y., Kayano, S., & Kihara, Y. (1985). A Fast 8K x 8 Mixed CMOS Static RAM. IEEE Transactions on Electron Devices, 32(9), 1792-1796. https://doi.org/10.1109/T-ED.1985.22199