A fast lock phase-locked loop using a continuous-time phase frequency detector

Jun Pan, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)

    Abstract

    A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

    Original languageEnglish
    Title of host publicationIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    Pages393-396
    Number of pages4
    DOIs
    Publication statusPublished - 2007
    EventIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan
    Duration: 2007 Dec 202007 Dec 22

    Other

    OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    CityTainan
    Period07/12/2007/12/22

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Pan, J., & Yoshihara, T. (2007). A fast lock phase-locked loop using a continuous-time phase frequency detector. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (pp. 393-396). [4450145] https://doi.org/10.1109/EDSSC.2007.4450145