A fast selector-based subtract-multiplication unit and its application to butterfly unit

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtractmultiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach.

    Original languageEnglish
    Pages (from-to)60-69
    Number of pages10
    JournalIPSJ Transactions on System LSI Design Methodology
    Volume4
    DOIs
    Publication statusPublished - 2011

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications

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    A fast selector-based subtract-multiplication unit and its application to butterfly unit. / Tsukamoto, Youhei; Yanagisawa, Masao; Ohtsuki, Tatsuo; Togawa, Nozomu.

    In: IPSJ Transactions on System LSI Design Methodology, Vol. 4, 2011, p. 60-69.

    Research output: Contribution to journalArticle

    @article{c0692a831cd4485abe76b6f3f50f63ef,
    title = "A fast selector-based subtract-multiplication unit and its application to butterfly unit",
    abstract = "Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute {"}subtractmultiplication{"}. In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92{\%}, compared to a conventional approach.",
    author = "Youhei Tsukamoto and Masao Yanagisawa and Tatsuo Ohtsuki and Nozomu Togawa",
    year = "2011",
    doi = "10.2197/ipsjtsldm.4.60",
    language = "English",
    volume = "4",
    pages = "60--69",
    journal = "IPSJ Transactions on System LSI Design Methodology",
    issn = "1882-6687",
    publisher = "Information Processing Society of Japan",

    }

    TY - JOUR

    T1 - A fast selector-based subtract-multiplication unit and its application to butterfly unit

    AU - Tsukamoto, Youhei

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    AU - Togawa, Nozomu

    PY - 2011

    Y1 - 2011

    N2 - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtractmultiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach.

    AB - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtractmultiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach.

    UR - http://www.scopus.com/inward/record.url?scp=82455181887&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=82455181887&partnerID=8YFLogxK

    U2 - 10.2197/ipsjtsldm.4.60

    DO - 10.2197/ipsjtsldm.4.60

    M3 - Article

    AN - SCOPUS:82455181887

    VL - 4

    SP - 60

    EP - 69

    JO - IPSJ Transactions on System LSI Design Methodology

    JF - IPSJ Transactions on System LSI Design Methodology

    SN - 1882-6687

    ER -