A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    Pages1083-1086
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur
    Duration: 2010 Dec 62010 Dec 9

    Other

    Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    CityKuala Lumpur
    Period10/12/610/12/9

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    Fast Fourier transforms

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T., & Togawa, N. (2010). A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 1083-1086). [5774956] https://doi.org/10.1109/APCCAS.2010.5774956

    A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. / Tsukamoto, Youhei; Yanagisawa, Masao; Ohtsuki, Tatsuo; Togawa, Nozomu.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 1083-1086 5774956.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tsukamoto, Y, Yanagisawa, M, Ohtsuki, T & Togawa, N 2010, A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 5774956, pp. 1083-1086, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, 10/12/6. https://doi.org/10.1109/APCCAS.2010.5774956
    Tsukamoto Y, Yanagisawa M, Ohtsuki T, Togawa N. A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. p. 1083-1086. 5774956 https://doi.org/10.1109/APCCAS.2010.5774956
    Tsukamoto, Youhei ; Yanagisawa, Masao ; Ohtsuki, Tatsuo ; Togawa, Nozomu. / A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2010. pp. 1083-1086
    @inproceedings{64c347c13a284cd9bb3d637b69392a51,
    title = "A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit",
    abstract = "Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute {"}subtract-multiplication{"}. In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92{\%}, compared to a conventional approach.",
    author = "Youhei Tsukamoto and Masao Yanagisawa and Tatsuo Ohtsuki and Nozomu Togawa",
    year = "2010",
    doi = "10.1109/APCCAS.2010.5774956",
    language = "English",
    isbn = "9781424474561",
    pages = "1083--1086",
    booktitle = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

    }

    TY - GEN

    T1 - A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

    AU - Tsukamoto, Youhei

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    AU - Togawa, Nozomu

    PY - 2010

    Y1 - 2010

    N2 - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.

    AB - Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.

    UR - http://www.scopus.com/inward/record.url?scp=79959259404&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=79959259404&partnerID=8YFLogxK

    U2 - 10.1109/APCCAS.2010.5774956

    DO - 10.1109/APCCAS.2010.5774956

    M3 - Conference contribution

    AN - SCOPUS:79959259404

    SN - 9781424474561

    SP - 1083

    EP - 1086

    BT - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

    ER -