A fastweighted adder by reducing partial product for reconstruction in super-resolution

Hiromine Yoshihara*, Masao Yanagisawa, Nozomu Togawa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


In recent years, it is quite necessary to convert conventional low-resolution images to high-resolution ones at low cost. Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder reduces its delay time by a maximum of 25.29% and its area to a maximum of 1/3, compared to conventional implementations.

Original languageEnglish
Pages (from-to)96-105
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Publication statusPublished - 2012


  • Reconstruction
  • Selector-logics
  • Super-resolution
  • Weighted adder

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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