A Fault-tolerant Hamiltonian-based Odd-Even Routing algorithm for Network-on-chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Network-on-chip (NoC) has emerged as an efficient communication method for Multi-Processor System-on-chips (MPSoCs). With the integration density increasing, there is more possibility that NoC is threaten by different faults in the network. In this paper, we propose a new fault-tolerant routing algorithm which takes advantage of improved Hamiltonian-based Odd-Even turn model and trys to reutilize some prohibited minimal paths. We configure our algorithm into adaptive and deterministic routings and unite them with an existing traffic-pattern detection mechanism to get a better performance in latency and throughput in different traffic patterns.

Original languageEnglish
Title of host publicationITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages217-222
Number of pages6
ISBN (Electronic)9784885523281
Publication statusPublished - 2020 Jul
Event35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
Duration: 2020 Jul 32020 Jul 6

Publication series

NameITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

Keywords

  • Hamiltonian path
  • Networks-on-Chip (NoC)
  • fault-tolerant routing
  • traffic pattern

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

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