A fine grain cooled logic architecture for low-power processors

Hiroyuki Matsubara, Takahiro Watanabe, Tadao Nakamura

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

Original languageEnglish
Pages (from-to)735-740
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE84-A
Issue number3
Publication statusPublished - 2001 Mar
Externally publishedYes

Fingerprint

Clocks
Electric power utilization
Logic
Power Consumption
Multiplier
Rails
Simulators
Hardware
Event-driven
Driver
Simulator
Architecture

Keywords

  • Cooled logic
  • Dual-rail logic
  • Low-power
  • Overlapped clock
  • Pass transistor

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

A fine grain cooled logic architecture for low-power processors. / Matsubara, Hiroyuki; Watanabe, Takahiro; Nakamura, Tadao.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 3, 03.2001, p. 735-740.

Research output: Contribution to journalArticle

@article{ef277bd1ec734eabb1381c2de7bd8b91,
title = "A fine grain cooled logic architecture for low-power processors",
abstract = "In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.",
keywords = "Cooled logic, Dual-rail logic, Low-power, Overlapped clock, Pass transistor",
author = "Hiroyuki Matsubara and Takahiro Watanabe and Tadao Nakamura",
year = "2001",
month = "3",
language = "English",
volume = "E84-A",
pages = "735--740",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "3",

}

TY - JOUR

T1 - A fine grain cooled logic architecture for low-power processors

AU - Matsubara, Hiroyuki

AU - Watanabe, Takahiro

AU - Nakamura, Tadao

PY - 2001/3

Y1 - 2001/3

N2 - In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

AB - In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

KW - Cooled logic

KW - Dual-rail logic

KW - Low-power

KW - Overlapped clock

KW - Pass transistor

UR - http://www.scopus.com/inward/record.url?scp=0035274026&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035274026&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0035274026

VL - E84-A

SP - 735

EP - 740

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 3

ER -