A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara; Noriaki Matsumoto; Kumiko Fujimori; Shuichi Kato

A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Shuichi Kato

Research output: Contribution to journal › Conference article › peer-review

Abstract

A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

Original language	English
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1990 Dec 1
Externally published	Yes
Event	Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA Duration: 1990 May 13 → 1990 May 16

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "A flexible multi-port RAM compiler for datapath",

abstract = "A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.",

author = "Hirofumi Shinohara and Noriaki Matsumoto and Kumiko Fujimori and Shuichi Kato",

year = "1990",

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journal = "Proceedings of the Custom Integrated Circuits Conference",

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AU - Shinohara, Hirofumi

AU - Matsumoto, Noriaki

AU - Fujimori, Kumiko

AU - Kato, Shuichi

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

AB - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

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AN - SCOPUS:0025694010

JO - Proceedings of the Custom Integrated Circuits Conference

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Y2 - 13 May 1990 through 16 May 1990

ER -

A flexible multi-port RAM compiler for datapath

Abstract

ASJC Scopus subject areas

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