A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara*, Noriaki Matsumoto, Kumiko Fujimori, Shuichi Kato

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

10 Citations (Scopus)


A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

Original languageEnglish
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1990 Dec 1
Externally publishedYes
EventProceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA
Duration: 1990 May 131990 May 16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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