Abstract
A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Custom Integrated Circuits Conference |
| Publisher | Publ by IEEE |
| Publication status | Published - 1990 |
| Externally published | Yes |
| Event | Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA Duration: 1990 May 13 → 1990 May 16 |
Other
| Other | Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 |
|---|---|
| City | Boston, MA, USA |
| Period | 90/5/13 → 90/5/16 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A flexible multi-port RAM compiler for datapath. / Shinohara, Hirofumi; Matsumoto, Noriaki; Fujimori, Kumiko; Kato, Shuichi.
Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, 1990.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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TY - GEN
T1 - A flexible multi-port RAM compiler for datapath
AU - Shinohara, Hirofumi
AU - Matsumoto, Noriaki
AU - Fujimori, Kumiko
AU - Kato, Shuichi
PY - 1990
Y1 - 1990
N2 - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.
AB - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.
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UR - http://www.scopus.com/inward/citedby.url?scp=0025694010&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0025694010
BT - Proceedings of the Custom Integrated Circuits Conference
PB - Publ by IEEE
ER -