A Flexible Multiport RAM Compiler for Data Path

Hirofumi Shinohara; Kumiko Fujimori; Yoshiki Tsujihashi; Shuichi Kato; Yasutaka Horiba; Noriaki Matsumoto; Hiroomi Nakao; Akiharu Tada

doi:10.1109/4.75013

A Flexible Multiport RAM Compiler for Data Path

Hirofumi Shinohara, Kumiko Fujimori, Yoshiki Tsujihashi, Shuichi Kato, Yasutaka Horiba, Noriaki Matsumoto, Hiroomi Nakao, Akiharu Tada

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.

Original language	English
Pages (from-to)	343-349
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	3
DOIs	https://doi.org/10.1109/4.75013
Publication status	Published - 1991 Mar
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.75013

Cite this

@article{0774599c2b994f469a98f941f921016f,

title = "A Flexible Multiport RAM Compiler for Data Path",

abstract = "A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.",

author = "Hirofumi Shinohara and Kumiko Fujimori and Yoshiki Tsujihashi and Shuichi Kato and Yasutaka Horiba and Noriaki Matsumoto and Hiroomi Nakao and Akiharu Tada",

year = "1991",

month = mar,

doi = "10.1109/4.75013",

language = "English",

volume = "26",

pages = "343--349",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A Flexible Multiport RAM Compiler for Data Path

AU - Shinohara, Hirofumi

AU - Fujimori, Kumiko

AU - Tsujihashi, Yoshiki

AU - Kato, Shuichi

AU - Horiba, Yasutaka

AU - Matsumoto, Noriaki

AU - Nakao, Hiroomi

AU - Tada, Akiharu

PY - 1991/3

Y1 - 1991/3

N2 - A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.

AB - A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.

UR - http://www.scopus.com/inward/record.url?scp=0026120432&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026120432&partnerID=8YFLogxK

U2 - 10.1109/4.75013

DO - 10.1109/4.75013

M3 - Article

AN - SCOPUS:0026120432

SN - 0018-9200

VL - 26

SP - 343

EP - 349

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 3

ER -

A Flexible Multiport RAM Compiler for Data Path

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this