A flexible multiport RAM compiler for data path

Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Yoshiki Tsujihashi, Hiroomi Nakao, Shuichi Kato, Yasutaka Horiba, Akiharu Tada

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b × 2048 words and 72 b × 512 words was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1K and 11.0 ns for 32K.

Original languageEnglish
Pages (from-to)343-349
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number3
DOIs
Publication statusPublished - 1991 Mar
Externally publishedYes

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Random access storage
Data storage equipment
Controllability
Aspect ratio
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shinohara, H., Matsumoto, N., Fujimori, K., Tsujihashi, Y., Nakao, H., Kato, S., ... Tada, A. (1991). A flexible multiport RAM compiler for data path. IEEE Journal of Solid-State Circuits, 26(3), 343-349. https://doi.org/10.1109/4.75013

A flexible multiport RAM compiler for data path. / Shinohara, Hirofumi; Matsumoto, Noriaki; Fujimori, Kumiko; Tsujihashi, Yoshiki; Nakao, Hiroomi; Kato, Shuichi; Horiba, Yasutaka; Tada, Akiharu.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 3, 03.1991, p. 343-349.

Research output: Contribution to journalArticle

Shinohara, H, Matsumoto, N, Fujimori, K, Tsujihashi, Y, Nakao, H, Kato, S, Horiba, Y & Tada, A 1991, 'A flexible multiport RAM compiler for data path', IEEE Journal of Solid-State Circuits, vol. 26, no. 3, pp. 343-349. https://doi.org/10.1109/4.75013
Shinohara H, Matsumoto N, Fujimori K, Tsujihashi Y, Nakao H, Kato S et al. A flexible multiport RAM compiler for data path. IEEE Journal of Solid-State Circuits. 1991 Mar;26(3):343-349. https://doi.org/10.1109/4.75013
Shinohara, Hirofumi ; Matsumoto, Noriaki ; Fujimori, Kumiko ; Tsujihashi, Yoshiki ; Nakao, Hiroomi ; Kato, Shuichi ; Horiba, Yasutaka ; Tada, Akiharu. / A flexible multiport RAM compiler for data path. In: IEEE Journal of Solid-State Circuits. 1991 ; Vol. 26, No. 3. pp. 343-349.
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