With ever growing demands of mobile devices, low power consumption has become essential for VLSI circuits. Since standard cell libraries are typically used in many parts of VLSI circuits, their performance has a strong impact on realizing high speed and low power VLSI circuits. One of the most promising approaches for reducing the power consumption of the circuit is lowering the supply voltage. However this causes an increase of imbalance between rise and fall delays especially for cells having transistor stacks. For mitigating this imbalance, this paper proposes a structure of standard cells where the P/N ratio of each cell can be independently customized for near-threshold operation in VLSI circuits. The structure cancels the imbalance between rise and fall delays at the expense of cell area. The experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.