A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages307-310
Number of pages4
Volume2005
Publication statusPublished - 2005
Externally publishedYes
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: 2005 Dec 52005 Dec 7

Other

OtherIEEE International Electron Devices Meeting, 2005 IEDM
CountryUnited States
CityWashington, DC, MD
Period05/12/505/12/7

Fingerprint

Dynamic random access storage
SOI (semiconductors)
floating
CMOS
wiring
Electric wiring
cells
compatibility
Networks (circuits)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

Cite this

Minami, Y., Shino, T., Sakamoto, A., Higashi, T., Kusunoki, N., Fujita, K., ... Nitayama, A. (2005). A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest (Vol. 2005, pp. 307-310). [1609336]

A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM. / Minami, Yoshihiro; Shino, Tomoaki; Sakamoto, Atsushi; Higashi, Tomoki; Kusunoki, Naoki; Fujita, Katsuyuki; Hatsuda, Kosuke; Ohsawa, Takashi; Aoki, Nobutoshi; Tanimoto, Hiroyoshi; Morikado, Mutsuo; Nakajima, Hiroomi; Inoh, Kazumi; Hamamoto, Takeshi; Nitayama, Akihiro.

IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. Vol. 2005 2005. p. 307-310 1609336.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Minami, Y, Shino, T, Sakamoto, A, Higashi, T, Kusunoki, N, Fujita, K, Hatsuda, K, Ohsawa, T, Aoki, N, Tanimoto, H, Morikado, M, Nakajima, H, Inoh, K, Hamamoto, T & Nitayama, A 2005, A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM. in IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. vol. 2005, 1609336, pp. 307-310, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, United States, 05/12/5.
Minami Y, Shino T, Sakamoto A, Higashi T, Kusunoki N, Fujita K et al. A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. Vol. 2005. 2005. p. 307-310. 1609336
Minami, Yoshihiro ; Shino, Tomoaki ; Sakamoto, Atsushi ; Higashi, Tomoki ; Kusunoki, Naoki ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Ohsawa, Takashi ; Aoki, Nobutoshi ; Tanimoto, Hiroyoshi ; Morikado, Mutsuo ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Takeshi ; Nitayama, Akihiro. / A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM. IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. Vol. 2005 2005. pp. 307-310
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abstract = "A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.",
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