A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Naoki Kusunoki, Hiroomi Nakajima, Mutsuo Morikado, Takashi Yamada, Kazumi Inoh, Atsushi Sakamoto, Tomoki Higashi, Katsuyuki Fujita, Kozuke Hatsuda, Takashi Ohsawa, Akihiro Nitayama

Research output: Contribution to journalArticle

22 Citations (Scopus)


A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.

Original languageEnglish
Pages (from-to)563-571
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number3
Publication statusPublished - 2007 Mar
Externally publishedYes



  • DRAM chips
  • Hot carriers
  • Silicon-on-insulator (SOI) technology

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hamamoto, T., Minami, Y., Shino, T., Kusunoki, N., Nakajima, H., Morikado, M., Yamada, T., Inoh, K., Sakamoto, A., Higashi, T., Fujita, K., Hatsuda, K., Ohsawa, T., & Nitayama, A. (2007). A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability. IEEE Transactions on Electron Devices, 54(3), 563-571. https://doi.org/10.1109/TED.2006.890597