A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Koichi Fujiwara, Shinya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distirbuted-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduces the number of slices by up to 47% and circuit delay by up to 16% compared with the conventional approach.

Original languageEnglish
Title of host publication2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages244-247
Number of pages4
EditionFebruary
ISBN (Electronic)9781479952304
DOIs
Publication statusPublished - 2015 Feb 5
Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
Duration: 2014 Nov 172014 Nov 20

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
NumberFebruary
Volume2015-February

Other

Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
CountryJapan
CityIshigaki Island, Okinawa
Period14/11/1714/11/20

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M., & Togawa, N. (2015). A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 (February ed., pp. 244-247). [7032765] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032765