TY - GEN
T1 - A floorplan-aware high-level synthesis technique with delay-variation tolerance
AU - Kawamura, Kazushi
AU - Hagio, Yuta
AU - Shi, Youhua
AU - Togawa, Nozomu
N1 - Funding Information:
Acknowledgment: This research is supported in part by NEDO and JSPS KAKENHI (Grant-in-Aid for JSPS Fellows).
Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/30
Y1 - 2015/9/30
N2 - For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.
AB - For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.
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U2 - 10.1109/EDSSC.2015.7285065
DO - 10.1109/EDSSC.2015.7285065
M3 - Conference contribution
AN - SCOPUS:84962163272
T3 - Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
SP - 122
EP - 125
BT - Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Y2 - 1 June 2015 through 4 June 2015
ER -