A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kazushi Kawamura, Yuta Hagio, Youhua Shi, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages122-125
Number of pages4
ISBN (Electronic)9781479983636
DOIs
Publication statusPublished - 2015 Sep 30
Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
Duration: 2015 Jun 12015 Jun 4

Publication series

NameProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Other

Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Country/TerritorySingapore
CitySingapore
Period15/6/115/6/4

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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