A floorplan-aware high-level synthesis technique with delay-variation tolerance

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.

    Original languageEnglish
    Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages122-125
    Number of pages4
    ISBN (Print)9781479983636
    DOIs
    Publication statusPublished - 2015 Sep 30
    Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
    Duration: 2015 Jun 12015 Jun 4

    Other

    Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    CountrySingapore
    CitySingapore
    Period15/6/115/6/4

    Fingerprint

    Scheduling
    Silicon
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Kawamura, K., Hagio, Y., Shi, Y., & Togawa, N. (2015). A floorplan-aware high-level synthesis technique with delay-variation tolerance. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 122-125). [7285065] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285065

    A floorplan-aware high-level synthesis technique with delay-variation tolerance. / Kawamura, Kazushi; Hagio, Yuta; Shi, Youhua; Togawa, Nozomu.

    Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 122-125 7285065.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kawamura, K, Hagio, Y, Shi, Y & Togawa, N 2015, A floorplan-aware high-level synthesis technique with delay-variation tolerance. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285065, Institute of Electrical and Electronics Engineers Inc., pp. 122-125, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 15/6/1. https://doi.org/10.1109/EDSSC.2015.7285065
    Kawamura K, Hagio Y, Shi Y, Togawa N. A floorplan-aware high-level synthesis technique with delay-variation tolerance. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 122-125. 7285065 https://doi.org/10.1109/EDSSC.2015.7285065
    Kawamura, Kazushi ; Hagio, Yuta ; Shi, Youhua ; Togawa, Nozomu. / A floorplan-aware high-level synthesis technique with delay-variation tolerance. Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 122-125
    @inproceedings{284bf4e41c9c4e0ebe65c821cdb4475b,
    title = "A floorplan-aware high-level synthesis technique with delay-variation tolerance",
    abstract = "For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3{\%} compared with conventional approaches.",
    author = "Kazushi Kawamura and Yuta Hagio and Youhua Shi and Nozomu Togawa",
    year = "2015",
    month = "9",
    day = "30",
    doi = "10.1109/EDSSC.2015.7285065",
    language = "English",
    isbn = "9781479983636",
    pages = "122--125",
    booktitle = "Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    TY - GEN

    T1 - A floorplan-aware high-level synthesis technique with delay-variation tolerance

    AU - Kawamura, Kazushi

    AU - Hagio, Yuta

    AU - Shi, Youhua

    AU - Togawa, Nozomu

    PY - 2015/9/30

    Y1 - 2015/9/30

    N2 - For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.

    AB - For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.

    UR - http://www.scopus.com/inward/record.url?scp=84962163272&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84962163272&partnerID=8YFLogxK

    U2 - 10.1109/EDSSC.2015.7285065

    DO - 10.1109/EDSSC.2015.7285065

    M3 - Conference contribution

    AN - SCOPUS:84962163272

    SN - 9781479983636

    SP - 122

    EP - 125

    BT - Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -