A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Koichi Fujiwara, Kazushi Kawamura, Shin Ya Abe, Masao Yanagisawa, Nozomu Togawa

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

    Original languageEnglish
    Pages (from-to)1392-1405
    Number of pages14
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE98A
    Issue number7
    DOIs
    Publication statusPublished - 2015 Jul 1

    Fingerprint

    High-level Synthesis
    Field Programmable Gate Array
    Field programmable gate arrays (FPGA)
    Module
    Costs
    Slice
    Latency
    Scheduling
    Design
    High level synthesis
    Experimental Results
    Processing
    Demonstrate

    Keywords

    • Floorplan
    • FPGA
    • High-level synthesis (HLS)
    • Interconnection delay
    • MUX

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    @article{847c6094fce4489db5ea74f8a3aaf930,
    title = "A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs",
    abstract = "Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47{\%} and latency by up to 22{\%} compared with conventional approaches while the number of required control steps is almost the same",
    keywords = "Floorplan, FPGA, High-level synthesis (HLS), Interconnection delay, MUX",
    author = "Koichi Fujiwara and Kazushi Kawamura and Abe, {Shin Ya} and Masao Yanagisawa and Nozomu Togawa",
    year = "2015",
    month = "7",
    day = "1",
    doi = "10.1587/transfun.E98.A.1392",
    language = "English",
    volume = "E98A",
    pages = "1392--1405",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "7",

    }

    TY - JOUR

    T1 - A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

    AU - Fujiwara, Koichi

    AU - Kawamura, Kazushi

    AU - Abe, Shin Ya

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2015/7/1

    Y1 - 2015/7/1

    N2 - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

    AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

    KW - Floorplan

    KW - FPGA

    KW - High-level synthesis (HLS)

    KW - Interconnection delay

    KW - MUX

    UR - http://www.scopus.com/inward/record.url?scp=84937622482&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84937622482&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E98.A.1392

    DO - 10.1587/transfun.E98.A.1392

    M3 - Article

    AN - SCOPUS:84937622482

    VL - E98A

    SP - 1392

    EP - 1405

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 7

    ER -