A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Kotaro Terada; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ISCAS.2015.7169100

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Kotaro Terada, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2129-2132
Number of pages	4
Volume	2015-July
ISBN (Print)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169100
Publication status	Published - 2015 Jul 27
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 2015 May 24 → 2015 May 27

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	15/5/24 → 15/5/27

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2015.7169100

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Terada, K., Yanagisawa, M., & Togawa, N. (2015). A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 2129-2132). [7169100] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169100

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. / Terada, Kotaro; Yanagisawa, Masao ; Togawa, Nozomu.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2015-July Institute of Electrical and Electronics Engineers Inc., 2015. p. 2129-2132 7169100.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Terada, K, Yanagisawa, M & Togawa, N 2015, A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 2015-July, 7169100, Institute of Electrical and Electronics Engineers Inc., pp. 2129-2132, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 15/5/24. https://doi.org/10.1109/ISCAS.2015.7169100

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abstract = "As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.",

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AB - As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.

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A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

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