A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

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    1 Citation (Scopus)

    Abstract

    As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages2129-2132
    Number of pages4
    Volume2015-July
    ISBN (Print)9781479983919
    DOIs
    Publication statusPublished - 2015 Jul 27
    EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
    Duration: 2015 May 242015 May 27

    Other

    OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
    CountryPortugal
    CityLisbon
    Period15/5/2415/5/27

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Terada, K., Yanagisawa, M., & Togawa, N. (2015). A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 2015-July, pp. 2129-2132). [7169100] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169100