A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and RDR (Regular-Distributed-Register) architecture has been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidates for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximum allowable distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously using the results of two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our algorithm reduces the latency by up to 28.6%, the number of registers by up to 37.5%, the number of multiplexers by up to 25.0%, compared to the conventional approaches.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages248-251
    Number of pages4
    Volume2015-February
    EditionFebruary
    DOIs
    Publication statusPublished - 2015 Feb 5
    Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
    Duration: 2014 Nov 172014 Nov 20

    Other

    Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
    CountryJapan
    CityIshigaki Island, Okinawa
    Period14/11/1714/11/20

    Fingerprint

    Scheduling
    High level synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Teradat, K., Yanagisawa, M., & Togawa, N. (2015). A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (February ed., Vol. 2015-February, pp. 248-251). [7032766] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032766

    A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. / Teradat, Kotaro; Yanagisawa, Masao; Togawa, Nozomu.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 2015-February February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 248-251 7032766.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Teradat, K, Yanagisawa, M & Togawa, N 2015, A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February edn, vol. 2015-February, 7032766, Institute of Electrical and Electronics Engineers Inc., pp. 248-251, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki Island, Okinawa, Japan, 14/11/17. https://doi.org/10.1109/APCCAS.2014.7032766
    Teradat K, Yanagisawa M, Togawa N. A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Vol. 2015-February. Institute of Electrical and Electronics Engineers Inc. 2015. p. 248-251. 7032766 https://doi.org/10.1109/APCCAS.2014.7032766
    Teradat, Kotaro ; Yanagisawa, Masao ; Togawa, Nozomu. / A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 2015-February February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 248-251
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    abstract = "In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and RDR (Regular-Distributed-Register) architecture has been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidates for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximum allowable distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously using the results of two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our algorithm reduces the latency by up to 28.6{\%}, the number of registers by up to 37.5{\%}, the number of multiplexers by up to 25.0{\%}, compared to the conventional approaches.",
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