A force directed partitioning algorithm for 3D floorplanning

Linquan Lyu, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Partitioning is very important to 3D IC physical design. Currently, hMetis (most famous partitioning software package) is widely used for partitioning. However, hMetis is for partitioning of hyper graphs. When the method is used for layer assignment of 3D floorplan/placement, some net might be too long. This paper develops a partitioning algorithm for 3D floorplan. The proposed combines a cost-based heuristic and force directed algorithm, which places the nodes considering attractive force and repulsive force, in order to solve the long net problem. We consider both the wire length and the number of TSVs in this work. The second part of the algorithm has two kinds according to the different emphasis. The experimental results demonstrated our algorithms can effectively reduce the wire length and the number of TSV. By comparing the experimental results of two focuses, we can get the differences and strengths of the two algorithms separately.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
PublisherIEEE Computer Society
Pages718-721
Number of pages4
Volume2017-October
ISBN (Electronic)9781509066247
DOIs
Publication statusPublished - 2018 Jan 8
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: 2017 Oct 252017 Oct 28

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period17/10/2517/10/28

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Keywords

  • 3D IC
  • Force-directed algorithm
  • IC partitioning
  • TSV
  • Wire length

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lyu, L., & Yoshimura, T. (2018). A force directed partitioning algorithm for 3D floorplanning. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 718-721). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252576