A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT

Q. I U Jingbang, Tianci Huang, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access, we achieve to further improve process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 145.0 MHz, processing up to 40 VGA images including memory operations. Compared with conventional work, hardware cost is slightly increased as trade-off for accelerated speed. High efficiency as 98.72% and high cover rate as 92.85% is kept by our proposal. Our proposal is suitable as a real-time SIFT system structure.

Original languageEnglish
Title of host publicationNCM 2009 - 5th International Joint Conference on INC, IMS, and IDC
Pages1668-1674
Number of pages7
DOIs
Publication statusPublished - 2009
EventNCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications - Seoul
Duration: 2009 Aug 252009 Aug 27

Other

OtherNCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications
CitySeoul
Period09/8/2509/8/27

Fingerprint

Particle accelerators
Field programmable gate arrays (FPGA)
Pixels
Hardware
Data storage equipment
Processing
Real time systems
Computer hardware
Clocks
Interpolation
Costs
Experiments

Keywords

  • Dual-pixel processing
  • Feature point detection
  • FPGA
  • Pipeline
  • SIFT

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

Cite this

Jingbang, Q. I. U., Huang, T., & Ikenaga, T. (2009). A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. In NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC (pp. 1668-1674). [5331581] https://doi.org/10.1109/NCM.2009.38

A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. / Jingbang, Q. I U; Huang, Tianci; Ikenaga, Takeshi.

NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC. 2009. p. 1668-1674 5331581.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jingbang, QIU, Huang, T & Ikenaga, T 2009, A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. in NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC., 5331581, pp. 1668-1674, NCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications, Seoul, 09/8/25. https://doi.org/10.1109/NCM.2009.38
Jingbang QIU, Huang T, Ikenaga T. A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. In NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC. 2009. p. 1668-1674. 5331581 https://doi.org/10.1109/NCM.2009.38
Jingbang, Q. I U ; Huang, Tianci ; Ikenaga, Takeshi. / A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC. 2009. pp. 1668-1674
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