A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications

Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The first single-chip design that supports real-time H.264/Advanced Video Coding decoding of $8$k (7680 x 4320) 60 frames/s is realized. It also supports multiview decoding for up to 32 720p views or 16 1080p views. To significantly improve the throughput and reduce the memory bandwidth requirement, frame-level parallelism is exploited for the proposed design. First, a frame dependency protection scheme enables frame-parallel decoding, by reusing multiple replicas of an existing design. This results in a system throughput of 2 Gpixels/s, at least 3.75 times better than previous chips. Moreover, a reference window synchronization scheme and a 2-level hybrid caching structure are proposed to achieve 44% memory bandwidth reduction of motion compensation, by utilizing frame-level data reuse. The bandwidth reduction results in 22% Dynamic Random-Access Memory power saving of the whole decoder.

Original languageEnglish
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOIs
Publication statusAccepted/In press - 2015 Feb 26

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Decoding
Bandwidth
Data storage equipment
Throughput
Motion compensation
Image coding
Synchronization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. / Zhou, Jinjia; Zhou, Dajiang; Zhu, Jiayi; Goto, Satoshi.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26.02.2015.

Research output: Contribution to journalArticle

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