A hard ware/S oft ware cosynthesis system for digital signal processor cores

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    16 Citations (Scopus)

    Abstract

    This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel multiple data memory buses (X-bus and Y-bus) hardware loop units addressing units and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

    Original languageEnglish
    Pages (from-to)2325-2327
    Number of pages3
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE82-A
    Issue number11
    Publication statusPublished - 1999

    Fingerprint

    Digital Signal Processor
    Digital signal processors
    Application programs
    kernel
    Computer hardware
    Reduced instruction set computing
    Hardware
    Unit
    Pipelines
    Hardware/software Partitioning
    Clocks
    Computer systems
    Compiler
    Software System
    Simulators
    Simulator
    Data storage equipment
    Cycle
    Target
    Software

    Keywords

    • Digital signal processing
    • Hardware/software cosynthesis
    • Hardware/software partitioning
    • Processor core

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

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    abstract = "This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel multiple data memory buses (X-bus and Y-bus) hardware loop units addressing units and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.",
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    author = "Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",
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    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 1999

    Y1 - 1999

    N2 - This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel multiple data memory buses (X-bus and Y-bus) hardware loop units addressing units and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

    AB - This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel multiple data memory buses (X-bus and Y-bus) hardware loop units addressing units and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

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    KW - Hardware/software cosynthesis

    KW - Hardware/software partitioning

    KW - Processor core

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