A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC

Lingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm 2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

Original languageEnglish
Pages (from-to)81-95
Number of pages15
JournalJournal of Signal Processing Systems
Volume50
Issue number1
DOIs
Publication statusPublished - 2008 Jan

Fingerprint

Arithmetic Coding
Hardware Architecture
Decoding
Encoding
Pipelines
Hardware
Binary
Reuse
Throughput
Partition
Clocks
Software
Context
Processing
Architecture

Keywords

  • CABAC
  • Codec
  • H.264/AVC
  • VLSI architecture

ASJC Scopus subject areas

  • Information Systems
  • Signal Processing
  • Theoretical Computer Science
  • Hardware and Architecture
  • Control and Systems Engineering
  • Modelling and Simulation

Cite this

A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC. / Li, Lingfeng; Song, Yang; Li, Shen; Ikenaga, Takeshi; Goto, Satoshi.

In: Journal of Signal Processing Systems, Vol. 50, No. 1, 01.2008, p. 81-95.

Research output: Contribution to journalArticle

Li, Lingfeng ; Song, Yang ; Li, Shen ; Ikenaga, Takeshi ; Goto, Satoshi. / A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC. In: Journal of Signal Processing Systems. 2008 ; Vol. 50, No. 1. pp. 81-95.
@article{a47eade83a524a4ea4a6b094f845d8bb,
title = "A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC",
abstract = "This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm 2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.",
keywords = "CABAC, Codec, H.264/AVC, VLSI architecture",
author = "Lingfeng Li and Yang Song and Shen Li and Takeshi Ikenaga and Satoshi Goto",
year = "2008",
month = "1",
doi = "10.1007/s11265-007-0117-y",
language = "English",
volume = "50",
pages = "81--95",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "1",

}

TY - JOUR

T1 - A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC

AU - Li, Lingfeng

AU - Song, Yang

AU - Li, Shen

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2008/1

Y1 - 2008/1

N2 - This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm 2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

AB - This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm 2 when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

KW - CABAC

KW - Codec

KW - H.264/AVC

KW - VLSI architecture

UR - http://www.scopus.com/inward/record.url?scp=42149182402&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=42149182402&partnerID=8YFLogxK

U2 - 10.1007/s11265-007-0117-y

DO - 10.1007/s11265-007-0117-y

M3 - Article

VL - 50

SP - 81

EP - 95

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 1

ER -