A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    Abstract

    This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Pages (from-to)830-836
    Number of pages7
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE87-A
    Issue number4
    Publication statusPublished - 2004 Apr

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    Hardware
    Software
    Unit
    Application programs
    Cycle
    Data Dependency
    Branch and Bound Algorithm
    Data storage equipment
    Timing
    Configuration
    Experimental Results
    Vertex of a graph
    Banks

    Keywords

    • Hardware/software cosynthesis
    • Heterogeneous datapaths and heterogeneous registers
    • Processor synthesis

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

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