Abstract
Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.
| Original language | English |
|---|---|
| Pages (from-to) | 1082-1092 |
| Number of pages | 11 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E86-A |
| Issue number | 5 |
| Publication status | Published - 2003 May |
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Keywords
- Content addressable memory
- Functional memory
- Hardware/software cosynthesis
- Hardware/software partitioning
- Micro processor core
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Information Systems
Cite this
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. / Togawa, Nozomu; Totsuka, Takao; Wakui, Tatsuhiko; Yanagisawa, Masao; Ohtsuki, Tatsuo.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 5, 05.2003, p. 1082-1092.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
AU - Togawa, Nozomu
AU - Totsuka, Takao
AU - Wakui, Tatsuhiko
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2003/5
Y1 - 2003/5
N2 - Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.
AB - Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.
KW - Content addressable memory
KW - Functional memory
KW - Hardware/software cosynthesis
KW - Hardware/software partitioning
KW - Micro processor core
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M3 - Article
AN - SCOPUS:0141903392
VL - E86-A
SP - 1082
EP - 1092
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 5
ER -