A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This paper proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which have only one functional unit for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
    Pages544-547
    Number of pages4
    Publication statusPublished - 2000
    Event2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin
    Duration: 2000 Dec 42000 Dec 6

    Other

    Other2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
    CityTianjin
    Period00/12/400/12/6

    Fingerprint

    Digital signal processors
    Hardware

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Togawa, N., Sakurai, T., Yanagisawa, M., & Ohtsuki, T. (2000). A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 544-547)

    A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. / Togawa, Nozomu; Sakurai, Takashi; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. 2000. p. 544-547.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Sakurai, T, Yanagisawa, M & Ohtsuki, T 2000, A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. in IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. pp. 544-547, 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems, Tianjin, 00/12/4.
    Togawa N, Sakurai T, Yanagisawa M, Ohtsuki T. A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. 2000. p. 544-547
    Togawa, Nozomu ; Sakurai, Takashi ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. 2000. pp. 544-547
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