A hardware/software partitioning algorithm for SIMD processor cores

K. Tachikake, Nozomu Togawa, Y. Miyaoka, Jinku Choi, Masao Yanagisawa, T. Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages135-140
    Number of pages6
    Volume2003-January
    ISBN (Print)0780376595
    DOIs
    Publication statusPublished - 2003
    EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
    Duration: 2003 Jan 212003 Jan 24

    Other

    OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
    CountryJapan
    CityKitakyushu
    Period03/1/2103/1/24

    Fingerprint

    Hardware
    Application programs

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    Cite this

    Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M., & Ohtsuki, T. (2003). A hardware/software partitioning algorithm for SIMD processor cores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2003-January, pp. 135-140). [1195006] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195006

    A hardware/software partitioning algorithm for SIMD processor cores. / Tachikake, K.; Togawa, Nozomu; Miyaoka, Y.; Choi, Jinku; Yanagisawa, Masao; Ohtsuki, T.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. p. 135-140 1195006.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tachikake, K, Togawa, N, Miyaoka, Y, Choi, J, Yanagisawa, M & Ohtsuki, T 2003, A hardware/software partitioning algorithm for SIMD processor cores. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2003-January, 1195006, Institute of Electrical and Electronics Engineers Inc., pp. 135-140, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 03/1/21. https://doi.org/10.1109/ASPDAC.2003.1195006
    Tachikake K, Togawa N, Miyaoka Y, Choi J, Yanagisawa M, Ohtsuki T. A hardware/software partitioning algorithm for SIMD processor cores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January. Institute of Electrical and Electronics Engineers Inc. 2003. p. 135-140. 1195006 https://doi.org/10.1109/ASPDAC.2003.1195006
    Tachikake, K. ; Togawa, Nozomu ; Miyaoka, Y. ; Choi, Jinku ; Yanagisawa, Masao ; Ohtsuki, T. / A hardware/software partitioning algorithm for SIMD processor cores. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. pp. 135-140
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