A hardware/software partitioning algorithm for SIMD processor cores

K. Tachikake, N. Togawa, Y. Miyaoka, Jinku Choi, M. Yanagisawa, T. Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages135-140
Number of pages6
ISBN (Electronic)0780376595
DOIs
Publication statusPublished - 2003 Jan 1
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2003-January

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03/1/2103/1/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M., & Ohtsuki, T. (2003). A hardware/software partitioning algorithm for SIMD processor cores. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 135-140). [1195006] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195006