Abstract
In this paper, a heuristic method for module sizing is proposed as a post-processing of the fixed-outline floorplanning. The heuristic method is based on horizontal and vertical slacks of blocks In the floorplan. By evaluating the distances of each block to the chip boundaries, x-slack and y-slack can be calculated. On the one hand, the heuristic focuses on the blocks has non-zero x-slack or non-zero y-slack but not both. These blocks will be first sorted by the amount of x / y-slack. The block having the most slack will be selected and reshaped, it has a potential to reduce the fixed-outline violation. On the other hand, the heuristic makes use of a marked flag for each block. After reshaping the block, the marked flag of the block will be set to 1. The slack of all the blocks will be recomputed and the focused blocks with marked flag 0 are reselected and sorted. If the set offocused blocks with marked flag 0 is empty, the marked flag of all the blocks will be reset to 0 and repeat the previous steps. If the fixed-outline constraint is not satisfied, we will repeat the procedure with defined maximum iteration number. Experimental results show that, the proposed heuristic could efficient achieve highly success rate without sacrificing much wire-length.
| Original language | English |
|---|---|
| Title of host publication | ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC |
| Pages | 738-741 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha Duration: 2009 Oct 20 → 2009 Oct 23 |
Other
| Other | 2009 8th IEEE International Conference on ASIC, ASICON 2009 |
|---|---|
| City | Changsha |
| Period | 09/10/20 → 09/10/23 |
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Keywords
- Fixed-outline floorplanning
- Module sizing
- Soft-module
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
A heuristic method for module sizing under fixed-outline constraints. / Zhang, Xiaolin; Chen, Song; Piao, Longfan; Yoshimura, Takeshi.
ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. p. 738-741 5351311.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A heuristic method for module sizing under fixed-outline constraints
AU - Zhang, Xiaolin
AU - Chen, Song
AU - Piao, Longfan
AU - Yoshimura, Takeshi
PY - 2009
Y1 - 2009
N2 - In this paper, a heuristic method for module sizing is proposed as a post-processing of the fixed-outline floorplanning. The heuristic method is based on horizontal and vertical slacks of blocks In the floorplan. By evaluating the distances of each block to the chip boundaries, x-slack and y-slack can be calculated. On the one hand, the heuristic focuses on the blocks has non-zero x-slack or non-zero y-slack but not both. These blocks will be first sorted by the amount of x / y-slack. The block having the most slack will be selected and reshaped, it has a potential to reduce the fixed-outline violation. On the other hand, the heuristic makes use of a marked flag for each block. After reshaping the block, the marked flag of the block will be set to 1. The slack of all the blocks will be recomputed and the focused blocks with marked flag 0 are reselected and sorted. If the set offocused blocks with marked flag 0 is empty, the marked flag of all the blocks will be reset to 0 and repeat the previous steps. If the fixed-outline constraint is not satisfied, we will repeat the procedure with defined maximum iteration number. Experimental results show that, the proposed heuristic could efficient achieve highly success rate without sacrificing much wire-length.
AB - In this paper, a heuristic method for module sizing is proposed as a post-processing of the fixed-outline floorplanning. The heuristic method is based on horizontal and vertical slacks of blocks In the floorplan. By evaluating the distances of each block to the chip boundaries, x-slack and y-slack can be calculated. On the one hand, the heuristic focuses on the blocks has non-zero x-slack or non-zero y-slack but not both. These blocks will be first sorted by the amount of x / y-slack. The block having the most slack will be selected and reshaped, it has a potential to reduce the fixed-outline violation. On the other hand, the heuristic makes use of a marked flag for each block. After reshaping the block, the marked flag of the block will be set to 1. The slack of all the blocks will be recomputed and the focused blocks with marked flag 0 are reselected and sorted. If the set offocused blocks with marked flag 0 is empty, the marked flag of all the blocks will be reset to 0 and repeat the previous steps. If the fixed-outline constraint is not satisfied, we will repeat the procedure with defined maximum iteration number. Experimental results show that, the proposed heuristic could efficient achieve highly success rate without sacrificing much wire-length.
KW - Fixed-outline floorplanning
KW - Module sizing
KW - Soft-module
UR - http://www.scopus.com/inward/record.url?scp=77949388841&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949388841&partnerID=8YFLogxK
U2 - 10.1109/ASICON.2009.5351311
DO - 10.1109/ASICON.2009.5351311
M3 - Conference contribution
AN - SCOPUS:77949388841
SN - 9781424438686
SP - 738
EP - 741
BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
ER -