A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    Abstract

    This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Pages (from-to)2655-2666
    Number of pages12
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE85-A
    Issue number12
    Publication statusPublished - 2002 Dec

    Fingerprint

    Energy Levels
    Electron energy levels
    Energy
    High-level Synthesis
    Delay Time
    Execution Time
    Clocks
    Voltage
    Hardware
    Module
    Experimental Results
    Electric potential
    Demonstrate

    Keywords

    • Area/time constraints
    • Energy optimization
    • High-level synthesis

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Information Systems
    • Electrical and Electronic Engineering

    Cite this

    @article{b2edea2d244d466e9e6950e4f701115c,
    title = "A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation",
    abstract = "This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.",
    keywords = "Area/time constraints, Energy optimization, High-level synthesis",
    author = "Shinichi Noda and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",
    year = "2002",
    month = "12",
    language = "English",
    volume = "E85-A",
    pages = "2655--2666",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

    AU - Noda, Shinichi

    AU - Togawa, Nozomu

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 2002/12

    Y1 - 2002/12

    N2 - This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

    AB - This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

    KW - Area/time constraints

    KW - Energy optimization

    KW - High-level synthesis

    UR - http://www.scopus.com/inward/record.url?scp=0037004702&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0037004702&partnerID=8YFLogxK

    M3 - Article

    AN - SCOPUS:0037004702

    VL - E85-A

    SP - 2655

    EP - 2666

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -