A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

    Original languageEnglish
    Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781467394987
    DOIs
    Publication statusPublished - 2016 May 31
    Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan, Province of China
    Duration: 2016 Apr 252016 Apr 27

    Other

    Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
    CountryTaiwan, Province of China
    CityHsinchu
    Period16/4/2516/4/27

    Fingerprint

    clocks
    Field programmable gate arrays (FPGA)
    Clocks
    synthesis
    Networks (circuits)
    modules
    High level synthesis
    wire
    Wire
    estimates

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality
    • Instrumentation

    Cite this

    Fujiwara, K., Kawamura, K., Yanagisawa, M., & Togawa, N. (2016). A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482547] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482547

    A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. / Fujiwara, Koichi; Kawamura, Kazushi; Yanagisawa, Masao; Togawa, Nozomu.

    2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482547.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Fujiwara, K, Kawamura, K, Yanagisawa, M & Togawa, N 2016, A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482547, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, Province of China, 16/4/25. https://doi.org/10.1109/VLSI-DAT.2016.7482547
    Fujiwara K, Kawamura K, Yanagisawa M, Togawa N. A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482547 https://doi.org/10.1109/VLSI-DAT.2016.7482547
    Fujiwara, Koichi ; Kawamura, Kazushi ; Yanagisawa, Masao ; Togawa, Nozomu. / A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016.
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    abstract = "High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24{\%} compared with conventional approaches.",
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    AU - Togawa, Nozomu

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    AB - High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

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