A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/VLSI-DAT.2016.7482547

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482547
Publication status	Published - 2016 May 31
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan, Province of China Duration: 2016 Apr 25 → 2016 Apr 27

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	16/4/25 → 16/4/27

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation

Access to Document

10.1109/VLSI-DAT.2016.7482547

Cite this

Fujiwara, K., Kawamura, K., Yanagisawa, M., & Togawa, N. (2016). A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482547] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482547

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. / Fujiwara, Koichi; Kawamura, Kazushi; Yanagisawa, Masao et al.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482547 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujiwara, K, Kawamura, K, Yanagisawa, M & Togawa, N 2016, A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482547, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, Province of China, 16/4/25. https://doi.org/10.1109/VLSI-DAT.2016.7482547

Fujiwara K, Kawamura K, Yanagisawa M , Togawa N. A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482547. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482547

Fujiwara, Koichi ; Kawamura, Kazushi ; Yanagisawa, Masao et al. / A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

@inproceedings{b18aee498d7047318a5c0b7d31dc1eac,

title = "A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration",

abstract = "High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.",

author = "Koichi Fujiwara and Kazushi Kawamura and Masao Yanagisawa and Nozomu Togawa",

note = "Funding Information: This research is supported in part by NEDO, Grant-in-aid for Sicentific Research (No. 25280017) and for JSPS Fellows, and Waseda University Grants for Special Research Projects (No. 2015K-148 and No. 2015B-171). Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482547",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

}

TY - GEN

T1 - A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

AU - Fujiwara, Koichi

AU - Kawamura, Kazushi

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

N1 - Funding Information: This research is supported in part by NEDO, Grant-in-aid for Sicentific Research (No. 25280017) and for JSPS Fellows, and Waseda University Grants for Special Research Projects (No. 2015K-148 and No. 2015B-171). Publisher Copyright: © 2016 IEEE.

PY - 2016/5/31

Y1 - 2016/5/31

N2 - High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

AB - High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

UR - http://www.scopus.com/inward/record.url?scp=84978438096&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84978438096&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2016.7482547

DO - 10.1109/VLSI-DAT.2016.7482547

M3 - Conference contribution

AN - SCOPUS:84978438096

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Y2 - 25 April 2016 through 27 April 2016

ER -

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this