A high-level synthesis system for digital signal processing based on data-flow graph enumeration

Nozomu Togawa, Takafumi Hisakl, Masao Yanagisawa, Tatsuo Ohtsuku

    Research output: Contribution to journalArticle

    Abstract

    This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

    Original languageEnglish
    Pages (from-to)2563-2575
    Number of pages13
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE81-A
    Issue number12
    Publication statusPublished - 1998

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    Keywords

    • Data-flow oriented process
    • Dataflow graph enumeration
    • High-level synthesis
    • Resource binding
    • Scheduling

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

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