A high-level synthesis system for digital signal processing based on data-flow graph enumeration

Nozomu Togawa, Takafumi Hisakl, Masao Yanagisawa, Tatsuo Ohtsuku

    Research output: Contribution to journalArticle

    Abstract

    This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

    Original languageEnglish
    Pages (from-to)2563-2575
    Number of pages13
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE81-A
    Issue number12
    Publication statusPublished - 1998

    Fingerprint

    Data flow graphs
    High-level Synthesis
    Flow Graphs
    Digital signal processing
    Data Flow
    Enumeration
    Signal Processing
    Hardware
    Computer hardware description languages
    Scheduling
    Performance Evaluation
    High level synthesis
    Synthesis
    Benchmark
    Resources
    Experimental Results

    Keywords

    • Data-flow oriented process
    • Dataflow graph enumeration
    • High-level synthesis
    • Resource binding
    • Scheduling

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    @article{1f57790ca4ea45ef83ba1f72e29fdde6,
    title = "A high-level synthesis system for digital signal processing based on data-flow graph enumeration",
    abstract = "This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.",
    keywords = "Data-flow oriented process, Dataflow graph enumeration, High-level synthesis, Resource binding, Scheduling",
    author = "Nozomu Togawa and Takafumi Hisakl and Masao Yanagisawa and Tatsuo Ohtsuku",
    year = "1998",
    language = "English",
    volume = "E81-A",
    pages = "2563--2575",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - A high-level synthesis system for digital signal processing based on data-flow graph enumeration

    AU - Togawa, Nozomu

    AU - Hisakl, Takafumi

    AU - Yanagisawa, Masao

    AU - Ohtsuku, Tatsuo

    PY - 1998

    Y1 - 1998

    N2 - This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

    AB - This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

    KW - Data-flow oriented process

    KW - Dataflow graph enumeration

    KW - High-level synthesis

    KW - Resource binding

    KW - Scheduling

    UR - http://www.scopus.com/inward/record.url?scp=0032315121&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0032315121&partnerID=8YFLogxK

    M3 - Article

    AN - SCOPUS:0032315121

    VL - E81-A

    SP - 2563

    EP - 2575

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -