A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

    Original languageEnglish
    Title of host publication2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
    Pages122-127
    Number of pages6
    DOIs
    Publication statusPublished - 2011
    Event2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut
    Duration: 2011 Oct 42011 Oct 7

    Other

    Other2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
    CityBeirut
    Period11/10/411/10/7

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    Keywords

    • high parallel
    • LDPC decoder
    • low power
    • matrix reordering

    ASJC Scopus subject areas

    • Signal Processing

    Cite this

    Xie, Q., He, Q., Peng, X., Cui, Y., Chen, Z., Zhou, D., & Goto, S. (2011). A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. In 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings (pp. 122-127). [6088961] https://doi.org/10.1109/SiPS.2011.6088961