A high performance and highly reliable dual gate CMOS with gate/n- overlapped LDD applicable to the cryogenic operation

Masahide Inuishi, Katsuyoshi Mitsui, Shigeru Kusunoki, Masahiro Shimizu, Katsuhiro Tsukamoto

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n+ poly gate and a surface channel PMOS with p+ poly gate whose source/drain and gate were salicided with low-resistance TiSi2. The gate/n- overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.

Original languageEnglish
Pages (from-to)773-776
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1989
Externally publishedYes

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Threshold voltage
Ion implantation
Cryogenics
cryogenics
CMOS
Networks (circuits)
Electric potential
low resistance
threshold voltage
ion implantation
electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A high performance and highly reliable dual gate CMOS with gate/n- overlapped LDD applicable to the cryogenic operation. / Inuishi, Masahide; Mitsui, Katsuyoshi; Kusunoki, Shigeru; Shimizu, Masahiro; Tsukamoto, Katsuhiro.

In: Unknown Journal, 1989, p. 773-776.

Research output: Contribution to journalArticle

Inuishi, Masahide ; Mitsui, Katsuyoshi ; Kusunoki, Shigeru ; Shimizu, Masahiro ; Tsukamoto, Katsuhiro. / A high performance and highly reliable dual gate CMOS with gate/n- overlapped LDD applicable to the cryogenic operation. In: Unknown Journal. 1989 ; pp. 773-776.
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