A high performance and highly reliable dual gate CMOS with gate/n- overlapped LDD applicable to the cryogenic operation

Masahide Inuishi*, Katsuyoshi Mitsui, Shigeru Kusunoki, Masahiro Shimizu, Katsuhiro Tsukamoto

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)


A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n+ poly gate and a surface channel PMOS with p+ poly gate whose source/drain and gate were salicided with low-resistance TiSi2. The gate/n- overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.

Original languageEnglish
Pages (from-to)773-776
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1989 Dec 1
Externally publishedYes
Event1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
Duration: 1989 Dec 31989 Dec 6

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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