A high-performance circuit design algorithm using data dependent approximation

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.

    Original languageEnglish
    Title of host publicationISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages95-96
    Number of pages2
    ISBN (Electronic)9781467393089
    DOIs
    Publication statusPublished - 2016 Dec 27
    Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
    Duration: 2016 Oct 232016 Oct 26

    Other

    Other13th International SoC Design Conference, ISOCC 2016
    CountryKorea, Republic of
    CityJeju
    Period16/10/2316/10/26

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Instrumentation

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  • Cite this

    Kawamura, K., Yanagisawa, M., & Togawa, N. (2016). A high-performance circuit design algorithm using data dependent approximation. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 95-96). [7799750] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799750