Abstract
This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.
Original language | English |
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Title of host publication | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 95-96 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
Publication status | Published - 2016 Dec 27 |
Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Other
Other | 13th International SoC Design Conference, ISOCC 2016 |
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Country | Korea, Republic of |
City | Jeju |
Period | 16/10/23 → 16/10/26 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation