A high performance digital neural processor design by Network on Chip architecture

Dong Yiping, Li Ce, Liu Hui, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a high performance neural processor by using a Network on Chip (NoC) architecture to solve the interconnection and performance problems in hardware neural networks. The proposed NoC-based neural processor is composed of 20 tiles in 45 2-D array, and each tile includes a Process Element (PE) and a packet switched router. In each PE, four neurons are implemented to achieve low communication load. The network is 2D torus topology, and it has a 32 G/s bandwidth and asynchronous clocking system. Our proposed neural processor is designed using 90-nm CMOS technology with one Poly and nine metals, and its performance is evaluated. As a result, it can achieve over 3.1 G Connection Per Second (CPS) of performance while power dissipation is 1.1317 W at 1.2 V supply-voltage and 25 mm2 chip area. Compared with the other existing hardware neural networks, the proposed processor can achieve low communication load and high performance, and it is reconfigurable and extendable.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages243-246
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu
Duration: 2011 Apr 252011 Apr 28

Other

Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
CityHsinchu
Period11/4/2511/4/28

Fingerprint

Tile
Neural networks
Hardware
Communication
Routers
Neurons
Energy dissipation
Topology
Bandwidth
Electric potential
Metals
Network-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yiping, D., Ce, L., Hui, L., & Watanabe, T. (2011). A high performance digital neural processor design by Network on Chip architecture. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 243-246). [5783621] https://doi.org/10.1109/VDAT.2011.5783621

A high performance digital neural processor design by Network on Chip architecture. / Yiping, Dong; Ce, Li; Hui, Liu; Watanabe, Takahiro.

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 243-246 5783621.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yiping, D, Ce, L, Hui, L & Watanabe, T 2011, A high performance digital neural processor design by Network on Chip architecture. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783621, pp. 243-246, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, 11/4/25. https://doi.org/10.1109/VDAT.2011.5783621
Yiping D, Ce L, Hui L, Watanabe T. A high performance digital neural processor design by Network on Chip architecture. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 243-246. 5783621 https://doi.org/10.1109/VDAT.2011.5783621
Yiping, Dong ; Ce, Li ; Hui, Liu ; Watanabe, Takahiro. / A high performance digital neural processor design by Network on Chip architecture. Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. pp. 243-246
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