A high performance HEVC de-blocking filter and SAO architecture for UHDTV decoder

Jiayi Zhu, Dajiang Zhou, Satoshi Goto

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4x4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8x8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 X 4320) @ 60fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.

Original languageEnglish
Pages (from-to)2612-2622
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE96-A
Issue number12
DOIs
Publication statusPublished - 2013

Fingerprint

Video Coding
Image coding
High Efficiency
High Performance
Filter
Data storage equipment
Image compression
Decoding
Pipelines
Pixels
Networks (circuits)
Processing
Architecture
Video Compression
Data Storage
Parallelism
Pixel
Integrate
Logic

Keywords

  • DBF
  • HEVC
  • Pipeline
  • SAO

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

A high performance HEVC de-blocking filter and SAO architecture for UHDTV decoder. / Zhu, Jiayi; Zhou, Dajiang; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E96-A, No. 12, 2013, p. 2612-2622.

Research output: Contribution to journalArticle

@article{470e29385d44439e8dcf98ed4d14fbbb,
title = "A high performance HEVC de-blocking filter and SAO architecture for UHDTV decoder",
abstract = "High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4x4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8x8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 X 4320) @ 60fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.",
keywords = "DBF, HEVC, Pipeline, SAO",
author = "Jiayi Zhu and Dajiang Zhou and Satoshi Goto",
year = "2013",
doi = "10.1587/transfun.E96.A.2612",
language = "English",
volume = "E96-A",
pages = "2612--2622",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - A high performance HEVC de-blocking filter and SAO architecture for UHDTV decoder

AU - Zhu, Jiayi

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2013

Y1 - 2013

N2 - High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4x4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8x8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 X 4320) @ 60fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.

AB - High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4x4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8x8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 X 4320) @ 60fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.

KW - DBF

KW - HEVC

KW - Pipeline

KW - SAO

UR - http://www.scopus.com/inward/record.url?scp=84889045914&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84889045914&partnerID=8YFLogxK

U2 - 10.1587/transfun.E96.A.2612

DO - 10.1587/transfun.E96.A.2612

M3 - Article

VL - E96-A

SP - 2612

EP - 2622

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -