A high performance LDPC decoder for IEEE802.11n standard

Wen Jit, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages127-128
Number of pages2
DOIs
Publication statusPublished - 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama
Duration: 2009 Jan 192009 Jan 22

Other

OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CityYokohama
Period09/1/1909/1/22

Fingerprint

Throughput
Message passing
Pipelines
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Jit, W., Abe, Y., Ikenaga, T., & Goto, S. (2009). A high performance LDPC decoder for IEEE802.11n standard. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 127-128). [4796465] https://doi.org/10.1109/ASPDAC.2009.4796465

A high performance LDPC decoder for IEEE802.11n standard. / Jit, Wen; Abe, Yuta; Ikenaga, Takeshi; Goto, Satoshi.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 127-128 4796465.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jit, W, Abe, Y, Ikenaga, T & Goto, S 2009, A high performance LDPC decoder for IEEE802.11n standard. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4796465, pp. 127-128, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796465
Jit W, Abe Y, Ikenaga T, Goto S. A high performance LDPC decoder for IEEE802.11n standard. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 127-128. 4796465 https://doi.org/10.1109/ASPDAC.2009.4796465
Jit, Wen ; Abe, Yuta ; Ikenaga, Takeshi ; Goto, Satoshi. / A high performance LDPC decoder for IEEE802.11n standard. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. pp. 127-128
@inproceedings{8992612e4f0748f0ac2354ba68d5887a,
title = "A high performance LDPC decoder for IEEE802.11n standard",
abstract = "In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11{\%} area reduction.",
author = "Wen Jit and Yuta Abe and Takeshi Ikenaga and Satoshi Goto",
year = "2009",
doi = "10.1109/ASPDAC.2009.4796465",
language = "English",
isbn = "9781424427482",
pages = "127--128",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - A high performance LDPC decoder for IEEE802.11n standard

AU - Jit, Wen

AU - Abe, Yuta

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

AB - In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

UR - http://www.scopus.com/inward/record.url?scp=64549145025&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64549145025&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2009.4796465

DO - 10.1109/ASPDAC.2009.4796465

M3 - Conference contribution

AN - SCOPUS:64549145025

SN - 9781424427482

SP - 127

EP - 128

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -