A high performance LDPC decoder for IEEE802.11n standard

Wen Jit; Yuta Abe; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/ASPDAC.2009.4796465

A high performance LDPC decoder for IEEE802.11n standard

Wen Jit^*, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	127-128
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796465
Publication status	Published - 2009 Apr 20
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: 2009 Jan 19 → 2009 Jan 22

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country/Territory	Japan
City	Yokohama
Period	09/1/19 → 09/1/22

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/ASPDAC.2009.4796465

Cite this

A high performance LDPC decoder for IEEE802.11n standard. / Jit, Wen; Abe, Yuta; Ikenaga, Takeshi et al.

Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 127-128 4796465 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jit, W, Abe, Y, Ikenaga, T & Goto, S 2009, A high performance LDPC decoder for IEEE802.11n standard. in Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009., 4796465, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 127-128, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796465

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abstract = "In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.",

author = "Wen Jit and Yuta Abe and Takeshi Ikenaga and Satoshi Goto",

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A high performance LDPC decoder for IEEE802.11n standard

Abstract

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Conference

ASJC Scopus subject areas

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