A high performance partially-parallel irregular LDPC decoder based on sum-delta message passing schedule

Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations, (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost, (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

Original languageEnglish
Pages (from-to)3622-3629
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE91-A
Issue number12
DOIs
Publication statusPublished - 2008

Fingerprint

Message passing
Message Passing
Irregular
Schedule
Throughput
High Performance
Synthesis
Message-passing Algorithms
LDPC Codes
Pipelining
Competitiveness
Sorting
Demonstrate
High Throughput
Decoding
Speedup
Trade-offs
Hardware
Binary
Decrease

Keywords

  • LDPC
  • Message passing algorithm

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

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abstract = "In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations, (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost, (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11{\%} area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.",
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N2 - In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations, (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost, (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

AB - In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations, (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost, (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

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