TY - JOUR
T1 - A high precision positive temperature circuit using DEM technique
AU - Liu, Hang
AU - Jin, Yu
AU - Li, Xin Hang
AU - Yu, Duli
AU - Han, Kedu
AU - Sun, Heming
N1 - Funding Information:
The work was supported by the research fund to the top scientific and technological innovation team from Beijing University of Chemical Technology (No. buctylkjcx06)
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - A novel positive temperature voltage circuit structure with dynamic element matching(DEM) calibration technology is proposed in this paper. The consistency of the thermometer output voltage is an important factor to ameliorate the precision in a thermometer circuit. The introduction of DEM technology reduces the mismatch error of the current source in the positive temperature voltage generating circuit, and improves the output voltage accuracy and voltage consistency. The circuit simulation results show that the positive temperature generating circuit using the DEM calibration circuit can reduce the offset voltage by 83.4% with good linearity property within -55°C to 125°C. The proposed positive temperature voltage circuit with DEM calibration is also considered to reduce power consumption and circuit complexity.
AB - A novel positive temperature voltage circuit structure with dynamic element matching(DEM) calibration technology is proposed in this paper. The consistency of the thermometer output voltage is an important factor to ameliorate the precision in a thermometer circuit. The introduction of DEM technology reduces the mismatch error of the current source in the positive temperature voltage generating circuit, and improves the output voltage accuracy and voltage consistency. The circuit simulation results show that the positive temperature generating circuit using the DEM calibration circuit can reduce the offset voltage by 83.4% with good linearity property within -55°C to 125°C. The proposed positive temperature voltage circuit with DEM calibration is also considered to reduce power consumption and circuit complexity.
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U2 - 10.1109/ASICON52560.2021.9620358
DO - 10.1109/ASICON52560.2021.9620358
M3 - Conference article
AN - SCOPUS:85122882646
SN - 2162-7541
JO - Proceedings of International Conference on ASIC
JF - Proceedings of International Conference on ASIC
T2 - 14th IEEE International Conference on ASIC, ASICON 2021
Y2 - 26 October 2021 through 29 October 2021
ER -