A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

Original languageEnglish
Title of host publication90 Symp VLSI Circuits
PublisherPubl by IEEE
Pages9-10
Number of pages2
Publication statusPublished - 1990
Externally publishedYes
Event1990 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 1990 Jun 71990 Jun 9

Other

Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period90/6/790/6/9

Fingerprint

Dynamic random access storage
Pipelines
Random access storage
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Furuyama, T., Kushiyama, N., Watanabe, Y., Ohsawa, T., Muraoka, K., & Nagahama, Y. (1990). A high random-access-data-rate 4MbDRAM with pipeline operation. In 90 Symp VLSI Circuits (pp. 9-10). Publ by IEEE.

A high random-access-data-rate 4MbDRAM with pipeline operation. / Furuyama, Tohru; Kushiyama, Natsuki; Watanabe, Yohji; Ohsawa, Takashi; Muraoka, Kazuyoshi; Nagahama, Yousei.

90 Symp VLSI Circuits. Publ by IEEE, 1990. p. 9-10.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Furuyama, T, Kushiyama, N, Watanabe, Y, Ohsawa, T, Muraoka, K & Nagahama, Y 1990, A high random-access-data-rate 4MbDRAM with pipeline operation. in 90 Symp VLSI Circuits. Publ by IEEE, pp. 9-10, 1990 Symposium on VLSI Circuits, Honolulu, HI, USA, 90/6/7.
Furuyama T, Kushiyama N, Watanabe Y, Ohsawa T, Muraoka K, Nagahama Y. A high random-access-data-rate 4MbDRAM with pipeline operation. In 90 Symp VLSI Circuits. Publ by IEEE. 1990. p. 9-10
Furuyama, Tohru ; Kushiyama, Natsuki ; Watanabe, Yohji ; Ohsawa, Takashi ; Muraoka, Kazuyoshi ; Nagahama, Yousei. / A high random-access-data-rate 4MbDRAM with pipeline operation. 90 Symp VLSI Circuits. Publ by IEEE, 1990. pp. 9-10
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